Emerging embedded Non-Volatile Memories (eNVM)

The era of AI is also the era of data. Being smart is to know how to absorb, process, sort, summarize, extrapolate a huge amount of data. The scaling of conventional memory technologies (SRAM and DRAM) is slowing down while compute efficiency keeps increasing with the improvement of architectures and design, which means that increasingly, memory is the bottleneck of big systems (DRAM centric) and small systems (counting on SRAM). Besides, a neuromorphic approach to compute has promises to generate much lower power solutions than existing systems, especially at the edge where the inputs can be event driven and scarce. A neuromorphic approach would benefit from two properties totally absent from SRAM and DRAM: non volatility and analog behavior or at least multi-level behavior.

Not all functions can be met by one single concept. All emerging memory technologies have a certain number of trade-offs that prevent these technologies to fit to all memory applications at the same time. The dream of universal memory, combining the non-volatility and the density of a storage cell with the performance and low power of a cache memory has been forgotten for a decade, every serious pathfinding work highlights the need to target a particular layer in the memory organization.

In the studied space, three main applications have been retained as potential fits for the developed technologies.

1. Embedded low power, non-volatile, read intensive memory. Similar to embedded Flash applications, it allows to store data or weights on chip for easy access in small low power systems. The two technologies considered in ANDANTE are OxRAM (in 22nm FDX technology) and Ferroelectric FET, demonstrated in 28nm CMOS technology node at Mb array level. OxRAM (Resistive RAM) is clearly showing its good potential for such an application with its cheap integration, and robustness to process variabilities. The well-known issue of RRAM is the trade-off between the energy put in the cell during set – reset, its stability, and variability. Therefore, the exact conditions need to be tuned for the application. FeFET also sees possibilities of meeting these specifications with an excellent read window and very low power due to field-based switching. The weakness of FeFET is linked to its interface between semiconductor and ferroelectric layer usually limiting its endurance, to be tackled in follow-up work.

Large scale integration in OxRAM

High endurance of Ferroeletric FET

2.  Last level cache applications. Any memory that could be higher density than SRAM while keeping the performance should be considered. The main contender in this case is SOT-MRAM technology, mostly due to its high reliability and VDD compatibility and large arrays, which were also integrated in 40nm logic node in ANDANTE. SOT-MRAM is also very promising in terms of performance and reliability. The challenges are to improve the write efficiency to further reduce the write energy and the bit cell design to significantly reduce cost as compared to SRAM.

“Unlimited endurance” Spin-Orbit Torque MRAM

3. Analog devices for machine learning applications, to store the weights and at the same time accumulate the response (current or charges) to deliver a multiply-accumulate function. This function is typically performed by classical CMOS circuits in today’s designs. In ANDANTE, three main technologies have been integrated in 300mm flow for this application: analog rheostatic phase change memory, ferroelectric FET and back-end compatible embedded DRAM based on IGZO channel. All three show the potential of window tuning to generate between 6 and 8 levels. eDRAM is not non-volatile but very wide bandgap semiconductor used in the back-end of line transistors will allow a longer refresh time than conventional DRAM cells. Ferroelectric FET tuning is due to partial polarization of the ferroelectric layer, which might be an issue when aggressively scaling the device and reducing the number of ferroelectric domains. In the rheostatic PCM, an extra conductive layer (lamina) was added as compared to conventional PCM to convert the volumetric material phase change into a linear resistive response.

Reliability and large-scale integration Phase Change Memory

The ANDANTE project showed that these technologies, in particular SOT-MRAM, OxRAM and FeFET can all be successfully integrated in advanced logic node at Mb level. All technologies but FeFET are integrated in BEOL. Only SOT-MRAM is fully Vdd compatible and doesn’t require any higher voltage. Yet, SOT-MRAM is likely the most expensive of the candidates due to the large bit cell area and fairly disruptive materials in the logic flow. OxRAM is the easier entry point in terms of cost, due to flow simplicity and material compatibility to regular logic flow. A last item is the potential capability of the cell to be integrated in 3 dimensions, similarly to 3D NAND today and considered for DRAM. Ferroelectric FET as well as 2T1C eDRAM are interesting concepts for these, since they don’t depend on fully crystalline semiconductors.

The future of edge AI lies in the co-optimization of algorithms, architecture, design but also new technologies to avoid any waste of resources and extract not only data but knowledge and wisdom from everything around us.